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K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 1 document title 4m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 0.4 0.5 remark advance history initial issue. data sheet, 1999 1. added ce don?t care mode during the data-loading and reading 1. revised real-time map-out algorithm(refer to technical notes) 2. removed erase suspend/resume mode 1. changed device name - km29w32000at -> K9F3208W0A-TCB0 - km29w32000ait -> k9f3208w0a-tib0 1. changed invalid block(s) marking method prior to shipping - the invalid block(s) information is written the 1st or 2nd page of the invalid block(s) with 00h data --->the invalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh data at the column address of 517. 2. changed se pin description - se is recommended to coupled to gnd or vcc and should not be toggled during reading or programming. 1.powerup sequence is added : recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences 2. ac parameter tclr(cle to re delay, min 50ns) is added. 3. ac parameter tar1 value : 150ns --> 20ns 4. #40 pin name : nse --> gnd v cc wp high ? ? ~ 2.5v ~ 2.5v ? we 1 m draft date april 10th 1998 april 10th 1999 july 23th 1999 sep. 15th 1999 july 17th 2000 july 23th 2001 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.intl.samsungsemi.com/memory/flash/datasheets.html.
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 2 4m x 8 bit nand flash memory the k9f3208w0a is a 4m(4,194,304)x8bit nand flash mem- ory with a spare 128k(131,072)x8bit. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation programs the 528-byte page in typical 250 m s and an erase operation can be performed in typi- cal 2ms on an 8k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/out- put as well as command inputs. the on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verification and margining of data. even the write-intensive systems can take advantage of the k9f3208w0a extended reliability of 1,000,000 program/erase cycles by providing ecc(error cor- rection code) with real time mapping-out algorithm. the k9f3208w0a is an optimum solution for large nonvolatile stor- age application such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility. general description features voltage supply : 2.7v ~ 5.5v organization - memory cell array : (4m + 128k)bit x 8bit - data register : (512 + 16)bit x8bit automatic program and erase - page program : (512 + 16)byte - block erase : (8k + 256)byte - status register 528-byte page read operation - random access : 10 m s(max.) - serial page access : 50ns(min.) fast write cycle time - program time : 250 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 1million program/erase cycles - data retention : 10 years command register operation 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) - forward type pin configuration note : connect all v cc, v cc q and v ss pins of each device to power supply outputs. do not leave v cc or v ss disconnected. v ss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc q i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c gnd r/ b re ce v cc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) standard type pin name pin function i/o0 ~ i/o7 data inputs/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect se spare area enable r/ b ready/busy output gnd ground input v cc power(2.7v ~ 5.5v) v cc q output butter power(2.7v ~ 5.5v) v ss ground n.c no connection pin description
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 3 512bytes 16bytes figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the sarting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * x can be high or low. * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 *x *x *x v cc x-buffers y-gating 32m + 1m bit command 2nd half page register & s/a nand flash array (512 + 16)byte x 8192 y-gating 1st half page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 21 a 0 - a 7 command ce re we cle ale wp i/0 0 i/0 7 v cc q v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 32m : 8k pages (= 512 blocks) 512bytes 8 bit 16bytes 1 block =16 pages = (8k + 256) byte i/o 0 ~ i/o 7 1 page = 528 bytes 1 block = 528 b x 16 pages = (8k + 256) bytes 1 device = 528bytes x 16pages x 512 blocks = 33 mbits column address row address (page address) page register
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 4 product introduction the k9f3208w0a is a 33mbit(34,603,008 bit) memory organized as 8192 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 16 pages formed by one nand structures, totaling 4,224 nand structures of 16 cells. the array organization is shown in figure 2. th e program and read operations are executed on a page basis, while the erase operation is executed on block basis. the memory array consists of 512 separately or grouped erasable 8k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9f3208w0a. the k9f3208w0a has addresses multiplexed into 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. the 4m byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: col - umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9f3208w0a. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. the 50h command is valid only when the se (pin 40) is low level. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h (2) - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o caution : any undefined command inputs are prohibited except for above command set of table 1.
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising ed ge of we with ale high. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling ed ge of re which also increments the internal column address counter by one. spare area enable( se ) the se input controls the access of the spare area. when se is high, the spare area is not accessible for reading or programming. se is recommended to be coupled to gnd or vcc and should not be toggled during reading or programming. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high- z when the chip is deselected or when the outputs are disabled. write protect( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. power line(v cc & v ccq ) the v ccq is the power supply for i/o interface logic. it is electrically isolated from main power line(v cc =2.7~5.5v) for supporting 5v tolerant i/o with 5v power supply at v ccq .
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 6 absolute maximum ratings note : 1. minimum dc voltage is -0.3v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc q+0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to +7.0 v temperature under bias K9F3208W0A-TCB0 t bias -10 to +125 c k9f3208w0a-tib0 -40 to +125 storage temperature t stg -65 to +150 c dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions vcc=2.7v ~ 3.6v vcc=3.6v ~ 5.5v unit min typ max min typ max operating current sequential read i cc 1 trc=80ns, ce =v il , i out =0ma - 10 20 - 15 30 ma program i cc 2 - - 10 20 - 15 30 erase i cc 3 - - 10 20 - 25 40 stand-by current(ttl) i sb 1 ce =v ih , wp = se =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp = se =0v/v cc - 10 50 - 10 50 m a input leakage current i li v in =0 to 5.5v - - 10 - - 10 output leakage current i lo v out =0 to 5.5v - - 10 - - 10 input high voltage v ih i/o pins 2.0 - v cc q+0.3 3.0 - v cc q+0.5 v except i/o pins 2.0 - v cc +0.3 3.0 - v cc +0.5 input low voltage, all inputs v il - -0.3 - 0.6 -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - 8 10 - ma recommended operating conditions (voltage reference to gnd, K9F3208W0A-TCB0:t a =0 to 70 c, k9f3208w0a-tib0:t a =-40 to 85 c) note : 1. vcc and vccq pins are separated each other. parameter symbol min typ. max unit supply voltage v cc 2.7 - 5.5 v supply voltage v cc q 2.7 - 5.5 v supply voltage v ss 0 0 0 v
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 7 mode selection note : 1. x can be v il or v ih 2. wp should be biased to cmos high or cmos low for standby. 3. when se is high, spare area is deselected. cle ale ce we re se wp mode h l l h x x read mode command input l h l h x x address input(3clock) h l l h x h write mode command input l h l h x h address input(3clock) l l l h l/h (3) h data input l l l h l/h (3) x sequential read & data output l l l h h l/h (3) x during read(busy) x x x x x l/h (3) h during program(busy) x x x x x x h during erase(busy) x x (1) x x x x l write protect x x h x x 0v/v cc (2) 0v/v cc (2) stand-by capacitance (t a =25 c, vcc=5.0v f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f3208w0a may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-market bad blocks. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. parameter symbol min typ. max unit valid block number n vb 502 508 512 blocks program/erase characteristics parameter symbol min typ max unit program time t prog - 0.25 1.5 ms number of partial program cycles in the same page nop - - 10 cycles block erase time t bers - 2 10 ms ac test condition (K9F3208W0A-TCB0:t a =0 to 70 c, k9f3208w0a-tib0:t a =-40 to 85 c, v cc =2.7v ~ 5.5v unless otherwise noted) parameter value vcc=2.7v ~ 3.6v vcc=3.6v ~ 5.5v input pulse levels 0.4v to 2.4v 0.4v to 3.4v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load 1 ttl gate and 1 ttl gate and cl=100pf cl=50pf(3.0v+/-10%),100pf(3.0v~3.6v)
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 8 ac characteristics for operation note : 1. the time to ready depends on the value of the pull-up resistor tied r/ b pin. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay(read id) t ar1 20 - ns ale to re delay(read cycle) t ar2 50 - ns cle to re delay t clr 50 - ns ce to re delay(id read) t cr 100 - ns ready to re low t rr 20 - ns re pulse width t rp 30 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 35 ns re high to output hi-z t rhz 15 30 ns ce high to output hi-z t chz - 20 ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) t cry - 50 +tr(r/ b ) (1) ns ce high hold time(at the last serial read) (2) t ceh 100 - ns re low to status output t rsto - 35 ns ce low to status output t csto - 45 ns re high to we low t rhw 0 - ns we high to re low t whr 60 - ns re access time(read id) t readid - 35 ns device resetting time (read/program/erase) t rst - 5/10/500 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 9 identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perfor- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guar- anteed to be a valid block, does not require error correction. nand flash technical notes all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh data at the column address of 517. since the invalid block information is also erasable in most cases, it is i mpos- sible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) b ased on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 1). a ny inten- tional erasure of the original invalid block information is prohibited. * figure 1. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table check "ffh" at the column address 517 of the 1st and 2nd page in the block
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 10 nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of m em- ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 11 erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 12 pointer operation of k9f3208w0a the k9f3208w0a has three modes to set the destination of the pointer. the pointer is set to "a" area by the "00h" command, to "b " area by the "01h" command, and to "c" area by the "50h" command. table 1 shows the destination of the pointer, and figure 2 show s the block diagram of its operations. examples of programming with successive pointer operation 50h "c" area (1) "a" area program "a" area address / data input table 1. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) table 2. pointer status after each operation * 01h command is valid just one time when it is used as a pointer for program/erase. * erase operation does not affect the pointer status. previous pointer status is maintained. operation pointer status after operation program reset power up with previous 00h, device is set to 00h plane with previous 01h, device is set to 00h plane* with previous 50h, device is set to 50h plane "00h" plane("a" area) "00h" plane("a" area) 00h 80h "a" area program 00h "a" area (2) "b" area program "b" area address / data input 01h 80h "a" area program 00h "a" area (3) "c" area program "c" area address / data input 50h 80h "c" area program 10h 80h 10h 10h 80h 10h 10h 80h 10h address / data input address / data input address / data input "a" area program "b" area program "c" area program "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 2. block diagram of pointer operation
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 13 system interface using ce don?t-care. ce we t wp t ch timing requirements : if ce is is exerted high during data-loading, tcs must be minimum 10ns and twc must be increased accordingly. t cs (min. 10ns) start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for a easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea (max. 45ns) ce re i/o 0 ~ 7 timing requirements : if ce is is exerted high during sequential data-reading, the falling edge of ce to valid data(tcea) must be kept greater than 45ns. figure 3. program operation with ce don?t-care. figure 4. read operation with ce don?t-care. must be held low during tr.
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 14 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 9 ~a 16 a 17 ~a 21 t cls t cs t clh t ch t wp t als t alh t ds t dh t cls t cs t wc t wc t wp t wp t wh t wh t als t alh t ds t dh t ds t dh t ds t dh t wp
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 15 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t ds t dh t ds t dh t wp t wh t wp t dh t wp * s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 trhz* dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz t rp ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 16 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t clr t clh t cs t wp t ch t ds t dh t rsto t ir t rhz* t chz* t whr t csto t cls read1 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout n+3 dout 527 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz t rb t cry t wc ? ? ? t ceh
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 17 read1 operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar2 t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout dout 527 m address a 0 ~ a 3 :valid address a 4 ~ a 7 :don't care 511+m dout 511+m+1 selected row start address m 512 16 t ar2 t r t wb t rr ? ?
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 18 sequential row read operation ce cle r/ b i/o 0 ~ 7 we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout 527 dout 0 dout 1 dout 2 dout 527 busy m+1 output n page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 21 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data sequential input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? ? ? ? ? ? ? ?
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 19 block erase operation (erase one block) ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 21 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers t wc t wc block address i/o 0 =0 successful erase ? manufacture & device id read operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech e3h t reaid t clr t ar1
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 20 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o pera- tion. three types of operations are available : random read, serial page read and sequential read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are trans- ferred to the data registers in less than 10 m s(t r ). the cpu can detect the completion of this data transfer(t r ) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re with ce staying low. high to low transitions of the re clock output the data starting from the selected column address up to the last column address(column 511 or 527 depending on state of se pin). after the data of last column address is clocked out, the next page is automatically selected for sequential read. waiting 10 m s again allows for reading of the selected page. the sequential read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 to 527 may be selectively accessed by writing the read2 command with se pin low. toggling se during operation is prohibited. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. unless the operation is aborted, the page address is automatically incremented for sequential read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 command(00h/01h) is needed to move the pointer back to the main area. figures 3 through 6 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 21 data output(sequential) (00h command) 1st half array 2nd half array ce cle ale r/ b we data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. i/o 0 ~ 7 re t r
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 21 figure 5. sequential row read1 operation figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 21 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field ( se =l, 00h command) 1st half array 2nd half array data field spare field 00h 01h a 0 ~ a 7 & a 9 ~ a 21 i/o 0 ~ 7 r/ b start add.(3cycle) start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) (a 4 ~ a 7 : don't care) 1st 2nd nth ( se =l, 01h command) 1st half array 2nd half array data field spare field 1st 2nd nth ( se =h, 00h command) 1st half array 2nd half array data field spare field 1st 2nd nth i/o 0 ~ 7 re t r t r t r t r ?
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 22 figure 6. sequential read2 operation ( se =fixed low) page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page registe r, fol- lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array. about the pointer operation, please refer to the attached technical notes.the serial data loadin g period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded. the page program confirm command(10h) initiates the programming process. writing 10h alone without perviously entering the serial data will not initiate the programming process. the internal write controller automatically executes the algorithms and t imings necessary for program and verify, thereby freeing the cpu for other tasks. once the program process starts, the read status regi s- ter command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6 ) of the status register. only the read status command and reset com- mand are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0 ) may be checked(figure 7). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the comm and register remains in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 21 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (16 byte) (16 byte) 1st half array 2nd half array data field spare field 1st 2nd nth (a 4 ~ a 7 : don't care) 1st figure 7. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 21 address & data input i/o 0 pass 528 byte data 10h 70h fail i/o 0 ~ 7 r/ b t r t r t r t prog ?
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 23 figure 8. block erase operation block erase the erase operation can erase on a block(8k byte) basis. block address loading is accomplished in two cycles initiated by an era se setup command(60h). only address a 13 to a 21 is valid while a 9 to a 12 is ignored. the addresses of the block to be erased to ffh. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequenc e of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(i/o 0 ) may be checked. figure 8 details the sequence. 60h block add. : a 9 ~ a 21 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. after writing 70h command to the command register, a read cycle outputs the contents of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. table2. read status register definition i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 24 figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (e3h) respectively. the command register remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h 00h ech e3h address. 1 cycle maker code device code t readid t ar1 t cea figure 10. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase modes, the reset operation will abort these operation. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. internal address registers are cleared to "0"s and data regist ers to "1"s. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset command is not necessary for normal operation. refer to figure 10 below. table3. device status after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b t rst t clr t whr
K9F3208W0A-TCB0, k9f3208w0a-tib0 flash memory 25 the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is begin after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 11). its val ue can be determined by the following guidance. ready/ busy v cc r/ b open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) fig 11 rp vs tr ,tf & rp vs ibusy ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp(min) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v
package dimensions flash memory 26 data protection the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences as shown in figure 12. the two step command sequence for program/erase provides additional software protection. figure 12. ac waveforms for power transition ~ 2.5v ~ 2.5v v cc wp high ? ? we 10 m s ? ?
package dimensions flash memory 27 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

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